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512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 512Mb C-die 72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 Registered DIMM Ordering Information
Part Number M393T6553CZ3-CD5/CC M393T6553CZA-CE7/E6/D5/CC M393T2953CZ3-CD5/CC M393T2953CZA-CE7/E6/D5/CC M393T2950CZ3-CD5/CC M393T2950CZA-CE7/E6/D5/CC M393T5750CZ3-CD5/CC M393T5750CZA-CE7/E6/D5/CC Density 512MB 512MB 1GB 1GB 1GB 1GB 2GB 2GB Organization 64Mx72 64Mx72 128Mx72 128Mx72 128Mx72 128Mx72 256Mx72 256Mx72 Component Composition 64Mx8(K4T51083QC)*9EA 64Mx8(K4T51083QC)*9EA 64Mx8(K4T51083QC)*18EA 64Mx8(K4T51083QC)*18EA 128Mx4(K4T51043QC)*18EA 128Mx4(K4T51043QC)*18EA 128Mx4(K4T51043QC)*36EA 128Mx4(K4T51043QC)*36EA Number of Rank 1 1 2 2 1 1 2 2
DDR2 SDRAM
Parity Register X O X O X O X O Height 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm
Note: "Z" of Part number(11th digit) stand for Lead-free products. Note: "3" of Part number(12th digit) stand for Dummy Pad PCB products. Note: "A" of Part number(12th digit) stand for Parity Register products.
Features
* Performance range
E7(DDR2-800) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 533 800 5-5-5 E6(DDR2-667) 400 533 667 5-5-5 D5(DDR2-533) 400 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK
* JEDEC standard 1.8V 0.1V Power Supply * VDDQ = 1.8V 0.1V * 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin * 4 Banks * Posted CAS * Programmable CAS Latency: 3, 4, 5 * Programmable Additive Latency: 0, 1 , 2 , 3 and 4 * Write Latency(WL) = Read Latency(RL) -1 * Burst Length: 4 , 8(Interleave/nibble sequential) * Programmable Sequential / Interleave Burst Mode * Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) * Off-Chip Driver(OCD) Impedance Adjustment * On Die Termination with selectable values(50/75/150 ohms or disable) * PASR(Partial Array Self Refresh) * Average Refresh Period 7.8us at lower than a TCASE 85C, 3.9us at 85C < TCASE < 95 C - support High Temperature Self-Refresh rate enable feature * Serial presence detect with EEPROM * DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8 * All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung's Device operation & Timing diagram.
Address Configuration
Organization 128Mx4(512Mb) based Module 64Mx8(512Mb) based Module Row Address A0-A13 A0-A13 Column Address A0-A9,A11 A0-A9 Bank Address BA0-BA1 BA0-BA1 Auto Precharge A10 A10
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Pin Configurations (Front side/Back side)
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DDR2 SDRAM
Front
A4 VDDQ A2 VDD KEY VSS VSS VDD NC/Par_In VDD A10/AP BA0 VDDQ WE CAS VDDQ S14 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41
Front
VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18
Pin
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Back
VSS DQ4 DQ5 VSS DM0/DQS9 NC/DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 NC/DQS10 VSS RFU RFU VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 NC/DQS11 VSS DQ22 DQ23
Pin
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Front
DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD NC NC/Err_Out VDDQ A11 A7 VDD A5
Pin
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Back
VSS DQ28 DQ29 VSS DM3/DQS12 NC/DQS12 VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8/DQS17 NC/DQS17 VSS CB6 CB7 VSS VDDQ CKE14 VDD NC NC VDDQ A12 A9 VDD A8 A6
Pin
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Pin
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
Back
VDDQ A3 A1 VDD CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A13 VDD VSS DQ36 DQ37 VSS DM4/DQS13 NC/DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS
Pin
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Front
VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC(TEST) VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL
Pin
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Back
DM5/DQS14 NC/DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DM6/DQS15 NC/DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC/DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
NC = No Connect, RFU = Reserved for Future Use 1. RESET (Pin 18) is connected to both OE of PLL and Reset of register. 2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) 3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity. 4. CKE1,S1 Pin is used for double side Registered DIMM.
Pin Description
Pin Name CK0 CK0 CKE0, CKE1 RAS CAS WE S0, S1 A0~A9, A11~A13 A10/AP BA0, BA1 SCL SDA SA0~SA2 Par_In Err_Out RESET Description Clock Inputs, positive line Clock inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge DDR2 SDRAM Bank Address Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD address Parity bit for the Address and Control bus Parity error found in the Address and Control bus Register and PLL control pin Pin Name ODT0~ODT1 DQ0~DQ63 CB0~CB7 DQS0~DQS8 DQS0~DQS8 DM(0~8),DQS(9~17) DQS9~DQS17 RFU NC TEST VDD VDDQ VSS VREF VDDSPD Description On die termination Data Input/Output Data check bits Input/Output Data strobes Data strobes, negative line Data Masks / Data strobes (Read) Data strobes (Read), negative line Reserved for Future Use No Connect Memory bus test tool (Not Connect and Not Useable on DIMMs) Core Power I/O Power Ground Input/Output Reference SPD Power
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Input/Output Functional Description
Symbol CK0 CK0 CKE0~CKE1 Type Input Input Input Function
DDR2 SDRAM
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored but previous operations continue. These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. I/O bus impedance control signals. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Reference voltage for SSTL_18 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank of four is activated. During a Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge. Data and Check Bit Input/Output pins Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM. Power and ground for the DDR SDRAM input buffers and core logic Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD to act as a pullup. Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt operation). The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchronized with the input clock ) Parity bit for the Address and Control bus. ( "1 " : Odd, "0 " : Even) Parity error found in the Address and Control bus Used by memory bus analysis tools (unused on memory DIMMs)
S0~S1
Input
ODT0~ODT1 RAS, CAS, WE VREF VDDQ BA0~BA1
Input Input Supply Supply Input
A0~A9,A10/AP A11~A13
Input
DQ0~63, CB0~CB7 DM0~DM8 VDD, VSS DQS0~DQS17 DQS0~DQS17 SA0~SA2 SDA SCL VDDSPD RESET Par_In Err_Out TEST
In/Out Input Supply In/Out In/Out Input In/Out Input Supply
Input Input Input In/Out
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx72 Module(populated as 1 rank of x8 DDR2 SDRAMs) M393T6553CZ3 / M393T6553CZA
RS0 DQS0 DQS0 DM0/DQS9 NC/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1/DQS10 NC/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2/DQS11 NC/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3/DQS12 NC/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8/DQS17 NC/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS
DQS4 DQS4 DM4/DQS13 NC/DQS13 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5/DQS14 NC/DQS14 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6/DQS15 NC/DQS15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7/DQS16 NC/DQS16 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS
D0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
D1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
D2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
D3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
Serial PD SCL WP A0 A1 A2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SDA
VDDSPD VDD/VDDQ VREF VSS
Serial PD D0 - D8 D0 - D8 D0 - D8
D8
SA0 SA1 SA2
Signals for Address and Command Parity Function (M393T6553CZA) 1:1 R E G I S T E R
RST
S0* BA0-BA1 A0-A13 RAS CAS WE CKE0 ODT0 RESET PCK7 PCK7
RSO-> CS : DDR2 SDRAMs D0-D8 RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8 RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8 RRAS -> RAS : DDR2 SDRAMs D0-D8 RCAS -> CAS : DDR2 SDRAMs D0-D8 RWE -> WE : DDR2 SDRAMs D0-D8 RCKE0 -> CKE : DDR2 SDRAMs D0-D8 RODT0 -> ODT0 : DDR2 SDRAMs D0-D8 * S0 connects to DCS and VDD connects to CSR on the register. CK0 CK0 RESET
VSS VSS PAR_IN 100K ohms
C0 C1
Register PPO QERR Err_Out
PAR_IN
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"
Notes : 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. Unless otherwise noted, resister values are 22 Ohms
P L L
OE
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8 PCK7 -> CK : Register PCK7 -> CK : Register
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx72 Module(populated as 2 rank of x8 DDR2 SDRAMs) M393T2953CZ3 / M393T2953CZA
RS1 RS0 DQS0 DQS0 DM0/DQS9 NC/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1/DQS10 NC/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DM2/DQS11 NC/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3/DQS12 NC/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8/DQS17 NC/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS
DQS4 DQS4 DM4/DQS13 NC/DQS13 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5/DQS14 NC/DQS14 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6/DQS15 NC/DQS15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7/DQS16 NC/DQS16 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS DM/ NU/ CS RDQS RDQS DQS DQS
D0
D9
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D13
D1
D10
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D14
D2
D11
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D15
D3
D12
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VDDSPD SDA VDD/VDDQ VREF VSS
D16
Serial PD SCL WP A0 A1 A2
Serial PD D0 - D17 D0 - D17 D0 - D17
C0 Register A C0 Register B VDD VSS C1 C1 VDD VDD RSO-> CS : DDR2 SDRAMs D0-D8 PPO RS1-> CS : DDR2 SDRAMs D9-D17 1:2 PPO PAR_IN PAR_IN PAR_IN RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17 R Err_Out QERR QERR 100K ohms RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17 E RRAS -> RAS : DDR2 SDRAMs D0-D17 G The resistors on Par_In, A13, A14, A15, BA2 and the RCAS -> CAS : DDR2 SDRAMs D0-D17 I signal line of Err_Out refer to the section: "Register RWE -> WE : DDR2 SDRAMs D0-D17 S Options for Unused Address inputs" RCKE0 -> CKE : DDR2 SDRAMs D0-D8 T RCKE1 -> CKE : DDR2 SDRAMs D9-D17 E RODT0 -> ODT0 : DDR2 SDRAMs D0-D8 R RODT1 -> ODT1 : DDR2 SDRAMs D9-D17 CK0 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17 P RST RESET** L PCK7** PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17 CK0 L PCK7** PCK7 -> CK : Register OE RESET PCK7 -> CK : Register * S0 connects to DCS and S0 connects to CSR on a Register, Notes : S1 connects to DCS and S0 connects to CSR on another Register. 1. DQ-to-I/O wiring may be changed per nibble. ** RESET, PCK7 and PCK7 connects to both Registers. 2. Unless otherwise noted, resister values are 22 Ohms Other signals connect to one of two Registers. 3. RS0 and RS1 alternate between the back and front sides of the DIMM S0* S1* BA0-BA1 A0-A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D17
SA0 SA1 SA2
Signals for Address and Command Parity Function (M393T2953CZA)
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx72 Module(populated as 1 rank of x4 DDR2 SDRAMs) M393T2950CZ3 / M393T2950CZA
VSS RS0 DQS0 DQS0
DM CS DQS DQS
DM0/DQS9 NC/DQS9
DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQS2
I/O 0 I/O 1 I/O 2 I/O 3
D0
DQ4 DQ5 DQ6 DQ7 DM1/DQS10 NC/DQS10
DQS DQS
I/O 0 I/O 1 I/O 2 I/O 3
D9
DM
CS
DM
CS
DQS DQS
I/O 0 I/O 1 I/O 2 I/O 3
D1
DQ12 DQ13 DQ14 DQ15 DM2/DQS11 NC/DQS11
I/O 0 I/O 1 I/O 2 I/O 3
D10
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ16 DQ17 DQ18 DQ19 DQS3 DQS3
I/O 0 I/O 1 I/O 2 I/O 3
D2
DQ20 DQ21 DQ22 DQ23 DM3/DQS12 NC/DQS12
I/O 0 I/O 1 I/O 2 I/O 3
D11
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ24 DQ25 DQ26 DQ27 DQS4 DQS4
I/O 0 I/O 1 I/O 2 I/O 3
D3
DQ28 DQ29 DQ30 DQ31 DM4/DQS13 NC/DQS13
I/O 0 I/O 1 I/O 2 I/O 3
Serial PD SCL WP A0 A1 A2 SDA
D12
DM
CS
DQS DQS
DM
CS
DQS DQS
SA0 SA1 SA2
DQ32 DQ33 DQ34 DQ35 DQS5 DQS5
I/O 0 I/O 1 I/O 2 I/O 3
D4
DQ36 DQ37 DQ38 DQ39 DM5/DQS14 NC/DQS14
I/O 0 I/O 1 I/O 2 I/O 3
D13
VDDSPD Serial PD D0 - D17 D0 - D17 D0 - D17
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ40 DQ41 DQ42 DQ43 DQS6 DQS6
I/O 0 I/O 1 I/O 2 I/O 3
D5
DQ44 DQ45 DQ46 DQ47 DM6/DQS15 NC/DQS15
I/O 0 I/O 1 I/O 2 I/O 3
VDD/VDDQ VREF VSS
D14
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ48 DQ49 DQ50 DQ51 DQS7 DQS7
I/O 0 I/O 1 I/O 2 I/O 3
D6
DQ52 DQ53 DQ54 DQ55 DM7DQS16 NC/DQS16
I/O 0 I/O 1 I/O 2 I/O 3
D15
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ56 DQ57 DQ58 DQ59 DQS8 DQS8
I/O 0 I/O 1 I/O 2 I/O 3
D7
DQ60 DQ61 DQ62 DQ63 DM8/DQS17 NC/DQS17
I/O 0 I/O 1 I/O 2 I/O 3
D16
DM
CS
DQS DQS
DM
CS
DQS DQS
CB0 CB1 CB2 CB3
I/O 0 I/O 1 I/O 2 I/O 3
D8
CB4 CB5 CB6 CB7
I/O 0 I/O 1 I/O 2 I/O 3
D17
Signals for Address and Command Parity Function (M393T2950CZA) S0* BA0-BA1 A0-A13 RAS CAS WE CKE0 ODT0 RESET** PCK7** PCK7** 1:2 R E G I S T E R
RST
RSO-> CS : DDR2 SDRAMs D0-D17 RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17 RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17 RRAS -> RAS : DDR2 SDRAMs D0-D17 RCAS -> CAS : DDR2 SDRAMs D0-D17 RWE -> WE : DDR2 SDRAMs D0-D17 RCKE0 -> CKE : DDR2 SDRAMs D0-D17 RODT0 -> ODT0 : DDR2 SDRAMs D0-D17 Notes : 1. DQ-to-I/O wiring may be changed per nibble. 2. Unless otherwise noted, resister values are 22 Ohms
VSS VDD PAR_IN 100K ohms
C0 C1
Register A PPO QERR
VDD VDD
C0 C1
Register B PPO QERR Err_Out
PAR_IN
PAR_IN
The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"
CK0 * S0 connects to DCS of Register1, CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD. ** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers. CK0 RESET
P L L
OE
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8 PCK7 -> CK : Register PCK7 -> CK : Register
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 2GB, 256Mx72 Module(populated as 2 rank of x4 DDR2 SDRAMs) M393T5750CZ3 / M393T5750CZA
VSS RS1 RS0 DQS0 DQS0
DM CS DQS DQS DM/ CS DQS DQS
DM0/DQS9 NC/DQS9
DM CS DQS DQS DM CS DQS DQS
Serial PD I/O 0 I/O 1 D9 I/O 2 I/O 3 I/O 0 I/O 1 D27 I/O 2 I/O 3 SCL WP A0 A1 A2 SDA
DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQS2
I/O 0 I/O 1 D0 I/O 2 I/O 3
I/O 0 I/O 1 D18 I/O 2 I/O 3
DQ4 DQ5 DQ6 DQ7 DM1/DQS10 NC/DQS10 DQ12 DQ13 DQ14 DQ15 DM2/DQS11 NC/DQS11
SA0 SA1 SA2
DM CS DQS DQS DM CS DQS DQS
DM
CS
DQS DQS
DM/
CS
DQS DQS
VDDSPD VDD/VDDQ VREF VSS
Serial PD D0 - D35 D0 - D35 D0 - D35
I/O 0 I/O 1 D1 I/O 2 I/O 3
I/O 0 I/O 1 D19 I/O 2 I/O 3
I/O 0 I/O 1 D10 I/O 2 I/O 3
I/O 0 I/O 1 D28 I/O 2 I/O 3
DM
CS
DQS DQS
DM/
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ16 DQ17 DQ18 DQ19 DQS3 DQS3
I/O 0 I/O 1 D2 I/O 2 I/O 3
I/O 0 I/O 1 D20 I/O 2 I/O 3
DQ20 DQ21 DQ22 DQ23 DM3/DQS12 NC/DQS12
I/O 0 I/O 1 D11 I/O 2 I/O 3
I/O 0 I/O 1 D29 I/O 2 I/O 3
Signals for Address and Command Parity Function (M393T5750CZA) VSS VDD C0 C1 Register A1 PPO QERR VDD VDD C0 C1 Register B1 PPO QERR 100K ohms VSS VDD C0 C1 Register A2 PPO QERR VDD VDD C0 C1 Register B2 PPO QERR Register A1 and A2 share the a part of Add/ Err_Out
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ24 DQ25 DQ26 DQ27 DQS4 DQS4
I/O 0 I/O 1 D3 I/O 2 I/O 3
I/O 0 I/O 1 D21 I/O 2 I/O 3
DQ28 DQ29 DQ30 DQ31 DM4/DQS13 NC/DQS13
I/O 0 I/O 1 D12 I/O 2 I/O 3
I/O 0 I/O 1 D30 I/O 2 I/O 3
PAR_IN
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ32 DQ33 DQ34 DQ35 DQS5 DQS5
I/O 0 I/O 1 D4 I/O 2 I/O 3
I/O 0 I/O 1 D22 I/O 2 I/O 3
DQ36 DQ37 DQ38 DQ39 DM5/DQS14 NC/DQS14
I/O 0 I/O 1 D13 I/O 2 I/O 3
I/O 0 I/O 1 D31 I/O 2 I/O 3
PAR_IN
PAR_IN
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ40 DQ41 DQ42 DQ43 DQS6 DQS6
I/O 0 I/O 1 D5 I/O 2 I/O 3
I/O 0 I/O 1 D23 I/O 2 I/O 3
DQ44 DQ45 DQ46 DQ47 DM6/DQS15 NC/DQS15
I/O 0 I/O 1 D14 I/O 2 I/O 3
I/O 0 I/O 1 D32 I/O 2 I/O 3
PAR_IN
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DQ48 DQ49 DQ50 DQ51 DQS7 DQS7
I/O 0 I/O 1 D6 I/O 2 I/O 3
I/O 0 I/O 1 D24 I/O 2 I/O 3
DQ52 DQ53 DQ54 DQ55 DM7DQS16 NC/DQS16
I/O 0 I/O 1 D15 I/O 2 I/O 3
I/O 0 I/O 1 D33 I/O 2 I/O 3
PAR_IN
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
Cmd input signal set. Register B1 and B2 share the rest part of Add/ Cmd input signal set. The resistors on Par_In, A13, A14, A15, BA2
DQ56 DQ57 DQ58 DQ59 DQS8 DQS8
I/O 0 I/O 1 D7 I/O 2 I/O 3
I/O 0 I/O 1 D25 I/O 2 I/O 3
DQ60 DQ61 DQ62 DQ63 DM8/DQS17 NC/DQS17
I/O 0 I/O 1 D16 I/O 2 I/O 3
I/O 0 I/O 1 D34 I/O 2 I/O 3
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
DM
CS
DQS DQS
and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"
CB0 CB1 CB2 CB3
I/O 0 I/O 1 D8 I/O 2 I/O 3
I/O 0 I/O 1 D26 I/O 2 I/O 3
CB4 CB5 CB6 CB7
I/O 0 I/O 1 D17 I/O 2 I/O 3
I/O 0 I/O 1 D35 I/O 2 I/O 3
S0* S1* BA0-BA1 A0-A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET** PCK7** PCK7** 1:2 R E G I S T E R
RST
RSO-> CS : DDR2 SDRAMs D0-D17 RS1-> CS : DDR2 SDRAMs D18-D35 RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35 RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35 RRAS -> RAS : DDR2 SDRAMs D0-D35 RCAS -> CAS : DDR2 SDRAMs D0-D35 RWE -> WE : DDR2 SDRAMs D0-D35 RCKE0 -> CKE : DDR2 SDRAMs D0-D17 RCKE1 -> CKE : DDR2 SDRAMs D18-D35 RODT0 -> ODT0 : DDR2 SDRAMs D0-D17 RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register. ** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
CK0 CK0 RESET
P L L
OE
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35 PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35 PCK7 -> CK : Register PCK7 -> CK : Register
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Absolute Maximum DC Ratings
Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Rating - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100
DDR2 SDRAM
Units V V V V C Notes 1 1 1 1 1, 2
Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Symbol VDD VDDL VDDQ VREF VTT Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Parameter Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V 4 4 1,2 3 Notes
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Operating Temperature Condition
Symbol TOPER Parameter Operating Temperature Rating 0 to 95 Units C
DDR2 SDRAM
Notes 1, 2, 3
Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 85 - 95 xC operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol VIH(DC) VIL(DC) Parameter DC input logic high DC input logic low Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes
Input AC Logic Level
Symbol VIH(AC) VIL(AC) Parameter AC input logic high AC input logic low DDR2-400, DDR2-533 Min. VREF + 0.250 Max. VREF - 0.250 DDR2-667, DDR2-800 Min. VREF + 0.200 VREF - 0.200 Max. Units V V
AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Condition Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VDDQ VIH(AC) min VSWING(MAX) VIH(DC) min VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = VREF - VIL(AC) max delta TF delta TR Rising Slew = VSS VIH(AC) min - VREF delta TR
< AC Input Test Signal Waveform >
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature) Symbol IDD0 Proposed Conditions
DDR2 SDRAM
Units mA
Notes
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0mA Slow PDN Exit MRS(12) = 1mA
IDD1
mA
IDD2P
mA
IDD2Q
mA
IDD2N
mA mA mA mA
IDD3P
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal Low Power
IDD4W
mA
IDD4R
mA
IDD5B
mA mA mA
IDD6
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions
mA
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M393T6553CZ3 / M393T6553CZA : 512MB(64Mx8 *9) Module
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6* IDD7 E7(800@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD E6(667@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD D5(533@CL=4) 1,240 1,405 562 760 775 750 348 1,000 1,620 1,525 1,780 72 2,660
DDR2 SDRAM
CC(400@CL=3) 1,130 1,285 522 710 715 720 338 930 1,410 1,340 1,720 72 2,570
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T2953CZ3 / M393T2953CZA : 1GB(64Mx8 *18) Module
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6* IDD7 E7(800@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD E6(667@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD D5(533@CL=4) 1,655 1,830 784 1,200 1,180 1,190 546 1,345 2,065 1,970 2,215 144 3,335 CC(400@CL=3) 1,575 1,770 724 1,130 1,150 1,130 516 1,325 1,865 1,785 2,125 144 3,095 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Notes
* IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M393T2950CZ3 / M393T2950CZA : 1GB(128Mx4 *18) Module
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6* IDD7 E7(800@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD E6(667@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD D5(533@CL=4) 2,060 2,370 784 1,200 1,180 1,190 546 1,480 2,650 2,600 3,160 144 5,000
DDR2 SDRAM
CC(400@CL=3) 1,980 2,310 724 1,130 1,150 1,130 516 1,460 2,360 2,370 3,070 144 4,760
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T5750CZ3 / M393T5750CZA : 2GB(128Mx4 *36) Module
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6* IDD7 E7(800@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD E6(667@CL=5) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD D5(533@CL=4) 2,980 3,340 1,238 2,060 2,030 2,050 922 2,350 3,630 3,430 4,090 288 6,330 CC(400@CL=3) 2,830 3,220 1,138 1,950 1,990 1,950 872 2,320 3,240 3,160 3,940 288 5,880 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Notes
* IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter Part-Number Input capacitance, CK and CK Input capacitance, CKE and CS Input capacitance, Addr,RAS,CAS,WE Input/output capacitance, DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min Max Min Max Min Max
DDR2 SDRAM
Min Max Units
M393T6553CZ3 M393T6553CZA 11 12 12 10
M393T2953CZ3 M393T2953CZA 11 12 12 10
M393T2950CZ3 M393T2950CZA 11 12 12 10
M393T5750CZ3 M393T5750CZA 11 12 12 10
pF
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 C < TOPER < 95 C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
DDR2 SDRAM
Refresh Parameters by Device Density
Parameter Refresh to active/Refresh command time Average periodic refresh interval tRFC tREFI 0 C TCASE 85C 85 C < TCASE 95C Symbol 256Mb 75 7.8 3.9 512Mb 105 7.8 3.9 1Gb 127.5 7.8 3.9 2Gb 195 7.8 3.9 4Gb 327.5 7.8 3.9 Units ns s s
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed Bin(CL - tRCD - tRP) Parameter tCK, CL=3 tCK, CL=4 tCK, CL=5 tRCD tRP tRC tRAS min 5 3.75 2.5 12.5 12.5 51.5 39 DDR2-800(E7) 5-5-5 max 8 8 8 70000 min 5 3.75 3 15 15 54 39 DDR2-667(E6) 5-5-5 max 8 8 8 70000 min 5 3.75 3.75 15 15 55 40 DDR2-533(D5) 4-4-4 max 8 8 8 70000 min 5 5 15 15 55 40 DDR2-400(CC) 3-3-3 max 8 8 70000 ns ns ns ns ns ns ns Units
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input
Symbol
tAC tDQSCK tCH tCL tHP tCK tDH(base) tDS(base) tIPW
DDR2-800 min
- 400 - 350 0.45 0.45 min(tCL,t CH) 2500 125 50 0.6 0.35 x tAC min 2* tAC min x x tHP tQHS - 0.25
DDR2-667 min
-450 -400 0.45 0.45 min(tCL, tCH) 3000 175 100 0.6 0.35 x tAC min 2*tAC min x x tHP tQHS -0.25
DDR2-533 min
-500 -450 0.45 0.45 min(tCL, tCH) 3750 225 100 0.6 0.35 x tAC min 2* tACmin x x tHP tQHS -0.25
DDR2-400 min
-600 -500 0.45 0.45 min(tCL, tCH) 5000 275 150 0.6 0.35 x tAC min 2* tACmin x x tHP tQHS -0.25
Units
ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK
Notes
max
400 350 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 200 300 x 0.25
max
+450 +400 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 240 340 x 0.25
max
+500 +450 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 300 400 x 0.25
max
+600 +500 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 350 450 x 0.25
DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK/CK tHZ DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK tLZ(DQS) tLZ(DQ)
DQS-DQ skew for DQS and associated DQ tDQSQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge tQHS tQH tDQSS
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Parameter
DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time
DDR2 SDRAM
DDR2-533 min
0.35 0.35 0.2 0.2 2 0.4 0.35 375 250 0.9 0.4 7.5 10 37.5 50 2 x x x 15 WR+tRP 7.5 7.5 tRFC + 10 200 x x 2 2 6 - AL x x x x x
Symbol
tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH(base) tIS(base) tRPRE tRPST tRRD tRRD tFAW tFAW tCCD tWR
DDR2-800 min
0.35 0.35 0.2 0.2 2 0.4 0.35 250 175 0.9 0.4 7.5 10 35 45 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC(min) 2 tAC(max) + 0.7 x x x x x x
DDR2-667 min
0.35 0.35 0.2 0.2 2 0.4 0.35 275 200 0.9 0.4 7.5 10 37.5 50 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 7 - AL 3 2 tAC(min) 2 tAC(max) +0.7
DDR2-400 min
0.35 0.35 0.2 0.2 2 0.4 0.35 475 350 0.9 0.4 7.5 10 37.5 50 2 15 WR+tRP 10 7.5 tRFC + 10 200 2 2 6 - AL x x x x x
Units
tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK
Notes
max
x x x x x 0.6 x x x 1.1 0.6 x x
max
x x x x x 0.6 x x x 1.1 0.6 x x
max
x x x x x 0.6 x x x 1.1 0.6 x x
max
x x x x x 0.6 x x x 1.1 0.6 x x
Auto precharge write recovery + precharge tDAL time Internal write to read command delay tWTR
Internal read to precharge command delay tRTP Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any nonread command Exit active power down to read command Exit active power down to read command (slow exit, lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW tXSNR tXSRD tXP tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tOIT tDelay
3
2 tAC(min) 2 tAC(max) +1
3
2 tAC(min) 2 tAC(max) +1
tCK ns ns tCK ns ns tCK tCK
2tCK + tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+ tAC(max) 2 (max)+1 2 (max)+1 2 (max)+1 2 +1 2.5 tAC(min) 2.5 tAC(max) + 0.6 2.5 tAC(min) 2.5 tAC(max) + 0.6 2.5
tAC(min)
2.5
tAC(max)+ 0.6
2.5 tAC(min)
2.5
tAC(max)+ 0.6
2.5tCK+ 2.5tCK+ 2.5tCK + tAC(min)+ tAC(min)+ 2.5tCK+tA tAC(min)+ tAC(min)+ tAC(max) tAC(max) tAC(max) 2 2 C(max)+1 2 2 +1 +1 +1 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH 12
ns ns
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Physical Dimensions: 64Mbx8 based 64Mx72 Module(1 Rank) M393T6553CZ3 / M393T6553CZA
DDR2 SDRAM
Units : Millimeters
133.35
2.70
Register
30.00
PLL 1.0 max
1.27 0.10
A 63.00
B 55.00
5.00 4.00
4.00
2.500.20
3.00 0.800.05
3.80
0.20 4.00
2.50
1.500.10
1.00
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QC
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Physical Dimensions: 64Mbx8/128Mbx4 based 128Mx72 Module(2/1 Ranks) M393T2953CZ3 / M393T2953CZA M393T2950CZ3 / M393T2950CZA
Units : Millimeters
133.35
4.00
Register
30.00
PLL 1.0 max 1.7 max
A 63.00
1.27 0.10
B 55.00
Register
5.00 4.00
4.00
2.500.20
3.00 0.800.05
3.80
0.20 4.00
2.50
1.500.10
1.00
Detail A
Detail B
The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QC / K4T51043QC
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Physical Dimensions: 128Mbx4 based 256Mx72 Module(2 Ranks) M393T5750CZ3 / M393T5750CZA
DDR2 SDRAM
Units : Millimeters
133.35
4.00
Register
PLL Register
30.00
1.0 max 1.7 max
A 63.00
1.27 0.10
B 55.00
Register
Register
5.00 4.00
4.00
2.500.20
3.00 0.800.05
3.80
0.20 4.00
2.50
1.500.10
1.00
Detail A
Detail B
The used device is 128M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51043QC
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
240 Pin DDR2 Registered DIMM Clock Topology
DDR2 SDRAM
0ns (nominal)
PLL DDR2 SDRAM OUT1 120 ohms
CK0
120 ohms IN
CK0
DDR2 SDRAM
Reg.A 120 ohms C Feedback In Feedback Out Reg.B OUTN
C
120 ohms
Note: 1. 2. 3. 4. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal). Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Revision History
Revision 1.0 (Apr. 2005)
- Initial Release
DDR2 SDRAM
Revision 1.1 (Jul. 2005)
- Revised the Ordering Information
Revision 1.2 (Aug. 2005)
- Revised the IDD Current Values
Rev. 1.2 Aug. 2005

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